8-12 April 2013
The University of Manchester
GB timezone

Trends in CPU design and its impact on the Grid

10 Apr 2013, 17:00
4.205 (The University of Manchester)


The University of Manchester

Presentations Community Platforms (Track Lead: P Solagna and M Drescher) Community Applications


Gareth Roy (UG)


This presentation will look at the current state-of-the-art in modern silicon process engineering and its direct relationship with modern CPU design. It will give an overview of the changes in modern processor design and an understaning of the industries focus on multi-core architectures. It will outline how changes in architecture design will impact the amount and diversity of processing power that is available on the Grid and how users can best leverage this.


This presentation will be useful for anyone who desires to understand the trends in modern processor design, particularly focusing on the impact that this will have on software engineering practices. Small and large VO's that produce simulation software will benefit from understanding some of the issues related to modern CPU architectures and the underlying physical reasons for these restrictions.

By understanding the underlying hardware and the way in which modern multi-core systems will work previously undiscovered bottlenecks can be identified and software can be enhanced to improve performance on the Grid.


With the increase in variety and availability of many- and multi-core architectures it becomes import to understand the motivation for moving to these designs and the impact that this will have on CPUs which are available on the Grid.

By looking at the moves of Intel and other manufactures to change their silicon process to FinFET designs (and the associated shift away from Bulk, SOI, FD-SOI, DG and others) we will explain the move to many-core architectures, and what the future could hold in terms of CPU and memory densities.

Focusing on the growth and development of multi-core CPU design we can see performance improvements and benefits that are inherent to the design of the CPU's themselves focusing on changing pipeline lengths, vectorization, HT, shared cores and other tricks played to squeeze performance from the Silicon.

As more and more CPU cores become available and densities increase, previously unnoticed bottlenecks in performance appear as shared resources become more heavily contested. An understanding of the underlying hardware issues will help inform a move to multi-threaded software, or resource aware software which will benefit the user community and the production environment it works on.

Primary author

Gareth Roy (UG)


Dr Andrew Washbrook (University of Edinburgh) Dr David Crooks (UG) Mark tomas Mitchell (UG) Prof Britton (UG) Sam Skipsey (UG) Stuart Purdie (UG)

Presentation Materials